Display Panel

ABSTRACT

The present disclosure relates to a display panel. More specifically, the display panel is configured to surround an opening area, includes a reflective electrode including an inclined surface, and therefore provides increased luminous efficiency.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.16/548,680 filed on Aug. 22, 2019 which claims the priority benefit ofRepublic of Korea Patent Application No. 10-2018-0163602, filed on Dec.17, 2018 in the Korean Intellectual Property Office, each of which isincorporated herein by reference in its entirety.

BACKGROUND Field of the Disclosure

The present disclosure relates to a display device and a display deviceincluding the same.

Description of the Background

As the advent of information society, there have been growing needs forvarious display panels for using in display devices, lighting devices,or the like. Among various display panels and display devices includingthe display panels, there is an increasing demand for organic lightemitting display panels which are advantageous in a reduction in overallweight and thickness because the organic light emitting display panelsdoes not require an additional light source.

However, when the organic light emitting display panel including anorganic light emitting layer emitting light is operated, a lightextraction efficiency of the organic light emitting display panel may bedecreased and corresponding luminance efficiency may be lowered becausesome of the light emitted from the organic light emitting layer cannotbe emitted outside the organic light emitting display panel, and becomestrapped inside the organic light emitting display device.

SUMMARY

Embodiments relate to a display panel comprising an overcoat layer, afirst electrode, a bank layer, an organic light emitting layer, a secondelectrode and a transistor. The overcoat layer has a first flat areahaving a first thickness, a second flat area having a second thicknessthicker than the first thickness, and an inclined area between the firstflat area and the second flat area. The first electrode is on the firstflat area, the inclined area and at least a part of the second flat areaof the overcoat layer. The first electrode is reflective of light andhas an inclined surface on the inclined area of the overcoat layer. Thebank layer covers a portion of the first flat area of the overcoatlayer, the inclined area of the overcoat layer, and at least a portionof the second flat area of the overcoat layer. The organic lightemitting layer is on the first electrode. The second electrode is on theorganic light emitting layer and the bank layer. At least part of atransistor overlaps the first flat area of the overcoat layer. Thetransistor has at least a terminal connected to the first electrodethrough a contact hole under the bank layer and located outside thefirst flat area.

In one or more embodiments, a thickness of the bank layer in the firstarea in a direction parallel to a surface of a substrate is less than orequal to 3.2μm.

In one or more embodiments, the thickness of the bank layer in the firstarea is larger than or equal to 0.1 μm.

In one or more embodiments, a difference between the first thickness andthe second thickness is larger than or equal to 0.7 μm.

In one or more embodiments, a difference between the first thickness andthe second thickness is less than or equal to 10 μm.

In one or more embodiments, the first area has a polygonal shape.

In one or more embodiments, the polygonal shape is an octagonal shape.

In one or more embodiments, the bank layer is transparent to visiblelight.

In one or more embodiments, the first electrode comprises a conductivemetal oxide layer and a reflective metal layer on the conductive metaloxide layer.

In one or more embodiments, the bank layer contacts a portion of thefirst electrode that is not covered by the bank in the first area.

In one or more embodiments, the organic light emitting layer extendsfrom the first area to the second area via the inclined area, the banklayer between the organic light emitting layer and the first electrodein the inclined area and the second area.

In one or more embodiments, a portion of the bank layer is on theinclined portion of the inclined surface of the first electrode, aportion of the organic light emitting layer on the portion of the banklayer is thinner than another portion of the organic light emittinglayer contacting the first electrode in the first area.

Embodiments also relate to a display panel including an overcoat layeron a substrate, a first electrode on the overcoat layer, a bank layercovering a portion of the first electrode but exposing at least anotherportion of the first electrode, an organic light emitting layer on thefirst electrode, and a second electrode on the organic light emittinglayer and the bank layer. The first electrode is reflective of light andhas an inclined surface. A first portion of light is emitted from theorganic light emitting layer through a flat area of the secondelectrode. A second portion of light is emitted from the organic lightemitting layer and reflected by the inclined area separated from thefirst portion of light.

In one or more embodiments, the portion of the first electrode contactsa transistor via a contact hole under the bank layer.

In one or more embodiments, the overcoat layer has a first thickness ata portion under the organic light emitting layer and has a secondthickness that is thicker than the first thickness at another portionnot under the organic light emitting layer.

In one or more embodiments, the first portion of light from a sub-pixelforms a main area on a viewing plane and the second portion of lightfrom the sub-pixel forms a supplemental area surrounding the main areain the viewing plane.

In one or more embodiments, the supplemental areas is formed for sub-pixels of only one or two colors.

In one or more embodiments, the supplemental area is discontinuous.

In one or more embodiments, the supplemental area has a shape of aclosed curve.

In one or more embodiments, at least one of brightness, shape and colorcoordinate of the supplemental area for the sub-pixel is different foranother sub-pixels of a different color.

In one or more embodiments, the display panel further comprisesauxiliary electrodes connected to a subset of sub-pixels, wherein theauxiliary electrodes are outside an area where the organic lightemitting layer is present.

In one or more embodiments, the display panel further comprises astorage capacitor at least a part of which overlaps the inclinedsurface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically illustrating a display deviceaccording to embodiments of the present disclosure.

FIG. 2 is a view schematically illustrating a system implementation ofthe display device according to embodiments of the present disclosure.

FIG. 3 is a view illustrating a structure of a subpixel in case thedisplay panel is configured with an organic light emitting diode (OLED)panel, according to embodiments of the present disclosure.

FIG. 4 is a cross-sectional view illustrating the display deviceaccording to embodiments of the present disclosure.

FIG. 5 is a view illustrating light emitted from an organic lightemitting layer of the display panel reflected from a second inclinedsurface, according to embodiments of the present disclosure.

FIG. 6 is an expanded cross-sectional view illustrating a part of thedisplay device according to embodiments of the present disclosure.

FIG. 7A is a view illustrating the display panel including an openingarea and a non-opening area, according to embodiments of the presentdisclosure.

FIG. 7B is a view illustrating an image of the display panel including afirst light emitting area, and a second light emitting area capture froma viewing plane, according to embodiments of the present disclosure.

FIG. 8 is a cross-sectional view illustrating the display deviceaccording to embodiments of the present disclosure.

FIG. 9 is a cross-sectional view illustrating a part of the displaydevice according to embodiments of the present disclosure.

DETAILED DESCRIPTION

Hereinafter, the present preferred embodiments of the disclosure will bedescribed in detail with reference to the accompanying drawings. Indenoting elements of the drawings by reference numerals, the sameelements will be referenced by the same reference numerals although theelements are illustrated in different drawings. Further, in thefollowing description of the disclosure, detailed description of knownfunctions and configurations incorporated herein may be omitted when itmay make the subject matter of the disclosure rather unclear.

Terms, such as first, second, A, B, (a), or (b) may be used herein todescribe elements of the disclosure. Each of the terms is not used todefine essence, order, sequence, or number of an element, but is usedmerely to distinguish the corresponding element from another element.When it is mentioned that an element is “connected” or “coupled” toanother element, it should be interpreted that another element may be“interposed” between the elements or the elements may be “connected” or“coupled” to each other via another element as well as that one elementis directly connected or coupled to another element. When it isdescribed that an element is “located”, “disposed”, “arranged”,“formed”, or the like over another element, it should be interpretedthat not only the element is directly contacted on the another element,but further another element may be “interposed” between the element andthe another element.

That is, it is noted that a connection or a coupling between an elementand another element may be described in such a manner that the elementis located, disposed, or formed over the another element, as anequivalent meaning.

FIG. 1 is a block diagram schematically illustrating a configuration ofa display device according to embodiments of the present disclosure. Thedisplay device according to embodiments of the present disclosure may bea display device with a display panel, or may further include or beincluded in a lighting device/apparatus/system, a luminescencedevice/apparatus/system, or the like. Hereinafter, for convenience ofdescription and ease of the understanding, discussions are conductedbased on the display device with the display panel. However, thefollowing description may be applicable to identically or similarly tovarious devices/apparatuses/systems with functionalities for displayingimages, such as, the lighting device/apparatus/system, the luminescencedevice/apparatus/system, or the like.

In accordance with embodiments of the present disclosure, the displaydevice may include a panel PNL for displaying images or emitting light,and a driving circuit (or driver) for driving the panel PNL.

The panel PNL may include a plurality of data lines DL and a pluralityof gate lines, and include a plurality of subpixels SP that is definedby the plurality of data lines DL and the plurality of gate lines GL andthat is arranged in a matrix form.

The plurality of data lines DL and the plurality of gate lines GL maycross each other and be arranged in the panel PNL. For example, theplurality of gate lines GL may be arranged in a first direction or onone of a row or a column, and the plurality of data lines DL may bearranged in a second direction or on the other of the row or the column.Hereinafter, for convenience of description and ease of theunderstanding, discussions are conducted on an example of the pluralityof gate lines GL arranged on a row and the plurality of data lines DLarranged on a column.

Depending on a structure or arrangements of subpixels, one or more typesof signal line may be disposed other than the plurality of data lines DLand the plurality of gate lines GL. For example, the display panel mayfurther include at least one driving voltage line, at least onereference voltage line, at least one common voltage line, or the like.

The panel PNL may be various types of panel, such as a liquid crystaldisplay LCD panel, an organic light emitting diode OLED panel, or thelike.

For example, one or more different types of signal line may be disposedin the panel PNL depending on a structure of subpixels, a type of panel(e.g., LCD panel, OLED panel, or the like), or the like. In the presentdisclosure, the signal line may denote a term including an electrode towhich a signal is applied.

The panel PNL may include an active area A/A for displaying an image anda non-active area N/A for not displaying an image. Here, the non-activearea N/A may be referred to as a bezel area or an edge area of the panelor the display device.

A plurality of subpixels SP is arranged in the active area A/A fordisplaying images.

At least one pad, such as conductive trace, electrically connected to adata driver DDR is disposed in the non-active area N/A, and a pluralityof data link lines may be disposed in the non-active area N/A forelectrically connecting the pad to the plurality of data lines DL. Inthis case, the plurality of data link lines may be a part of theplurality of data lines DL extending to the non-active area N/A, or beseparate patterns electrically connected to the plurality of data linesDL.

In addition, the non-active area N/A further may includegate-driving-related lines for delivering a voltage (signal) needed fordriving at least one gate of at least one transistor for driving atleast one subpixel from the pad electrically connected to the datadriver DDR to a gate driver GDR. For example, the gate-driving-relatedlines may include clock lines for delivering clock signals, gate voltagelines for delivering gate voltages (VGH, VGL), gate driving controlsignal lines for delivering various control signals needed forgenerating scan signals, or the like. The gate-driving-related lines arearranged in the non- active area N/A, unlike gate lines GL arranged inthe active area A/A.

The driving circuit may include the data driver DDR for driving theplurality of data lines DL, the gate driver GDR for driving theplurality of gate lines GL, and a controller CTR for controlling thedata driver DDR and the gate driver GDR.

The data driver DDR may drive the plurality of data lines DL byoutputting data voltages to the plurality of data lines DL.

The gate driver GDR may drive the plurality of gate lines GL byoutputting scan signals to the plurality of gate lines GL.

The controller CTR may provide various control signals DCS, GCS neededfor driving and/or operating the data driver DDR and the gate driverGDR, and control the driving and/or operating of the data driver DDR andthe gate driver GDR. In addition, the controller CTR may provide imagedata DATA to the data driver DDR.

The controller CTR starts scanning operation according to timingprocessed in each frame, converts image data input from other devices orimage providing sources to a data signal form used in the data driverDDR and then outputs resulting image data from the converting, andcontrols the driving of at least one data line at a pre-configured timealigned with the scanning operation.

In order to control the data driver DDR and the gate driver GDR, thecontroller CTR receives a timing signal, such as, a vertical synchronoussignal Vsync, a horizontal synchronous signal Hsync, an input dataenable DE signal, a clock signal CLK, or the like, from other devices orimage providing sources, such as, a host system, and generates variouscontrol signals and outputs the generated signals to the data driver DDRand the gate driver GDR.

For example, to control the gate driver GDR, the controller CTR outputsvarious gate control signals GCS including a gate start pulse GSP, agate shift clock GSC, a gate output enable signal GOE, or the like.

In addition, to control data driver(DDR), the controller CTR outputsvarious data control signals DCS including a source start pulse SSP, asource sampling clock SSC, a source output enable signal SOE, or thelike.

The controller CTR may be a timing controller used in the typicaldisplay technology or a control apparatus/device capable of additionallyperforming other control functionalities in addition to the typicalfunction of the timing controller.

The controller CTR may be implemented as a separate unit from the datadriver DDR, or integrated with the data driver DDR and implemented as anintegrated circuit.

The data driver DDR receives image data DATA form the controller CTR,and provides data voltages to the plurality of data lines DL. Thus it ispossible for the data driver DDR to drive the plurality of data linesDL. Herein, the data driver DDR may also be referred to as a “sourcedriver.”

The data driver DDR may transmit various signals to and/or receive themfrom the controller CTR through various interfaces.

The gate driver GDR sequentially drives the plurality of gate lines GLby sequentially providing scan signals to a plurality of gate lines GL.Herein, the gate driver GDR may also be referred to as a “scan driver.”

According to controlling of the controller CTR, the gate driver GDRsequentially provide a scan signal, such as an on-voltage or anoff-voltage to the plurality of gate lines GL.

When a specific gate line is asserted by a scan signal from the gatedriver GDR, the data driver DDR converts image data received from thecontroller into analog data voltages and provides the resulted analogdata voltages to the plurality of data lines DL.

The data driver DDR may be located on, but not limited to, only one side(e.g., top side or bottom side) of the panel PNL, or in someembodiments, be located on, but not limited to, two sides (e.g., topside and bottom side) of the panel PNL according to driving schemes,panel design schemes, or the like.

The gate driver GDR may be located on, but not limited to, only one side(e.g., left side or right side) of the panel PNL, or in someembodiments, be located on, but not limited to, two sides (e.g., leftside and right side) of the panel PNL according to driving schemes,panel design schemes, or the like.

The data driver DDR may be implemented by including one or more sourcedriver integrated circuits SDIC.

Each source driver integrated circuits SDIC may include a shiftregister, a latch circuit, a digital to analog converter DAC, an outputbuffer, or the like. In some embodiments, the data driver DDR mayfurther include one or more analog to digital converters ADC.

Each source driver integrated circuit SDIC may be connected to the pad,such as a bonding pad, of the panel PNL in a tape automated bonding TABtype or a chip on glass COG type, or be directly disposed on the panelPNL. In some embodiments, each source driver integrated circuit SDIC maybe integrated and disposed on the panel PNL. In addition, each sourcedriver integrated circuit SDIC may be implemented in a chip on filmtype. In this case, each source driver integrated circuit SDIC may bemounted on a circuit film and electrically connected to the data linesDL arranged in the panel PNL through the circuit film.

The gate driver GDR may include a plurality of gate driving circuitsGDC. Herein, the plurality of gate driving circuits GDC each maycorrespond to the respective plurality of gate lines GL.

Each gate driving circuit GDC may include a shift register, a levelshifter, and the like.

Each gate driving circuit GDC may be connected to the pad, such as abonding pad, of the panel PNL in a tape automated bonding TAB type or achip on glass COG type. In addition, each gate driving circuit GDC maybe implemented in a chip on film type. In this case, each gate drivingcircuit GDC may be mounted on a circuit film and electrically connectedto the gate lines GL arranged in the panel PNL through the circuit film.In addition, each gate driving circuit GDC may be integrated into thepanel PNL in a gate in panel GIP type. That is, each gate drivingcircuit GDC may be directly formed in the panel PNL.

FIG. 3 is a view illustrating a structure of a subpixel arranged in anorganic light emitting diode OLED panel, according to embodiments of thepresent disclosure. Referring to FIG. 3, each subpixel SP may beimplemented by electronic elements arranged in the OLED panel 110including, but not limited to, an organic light emitting diode OLED, adriving transistor DRT for driving the organic light emitting diodeOLED, a switching transistor O-SWT electrically connected between afirst node N1 of the driving transistor DRT and a corresponding dataline DL, a storage capacitor Cst electrically connected between thefirst node N1 and a second node N2 of the driving transistor DRT, or thelike.

The organic light emitting diode OLED may include an anode electrode, anorganic light emitting layer, a cathode electrode, and the like.

FIG. 2 is a view schematically illustrating a system implementation ofthe display device according to embodiments of the present disclosure.Referring to FIG. 2, in a display device according to embodiments of thepresent disclosure, a data driver DDR may be implemented in the chip onfilm COF type of various types, such as, TAB, COG, COF, GIP, or thelike. Also, a gate driver GDR may be implemented in the gate in panelGIP type of various types, such as, TAB, COG, COF, GIP, or the like.

The data driver DDR may be implemented as one or more source driverintegrated circuits SDIC. FIG. 2 shows an embodiment in which the datadriver DDR is implemented as a plurality of source driving integratedcircuits SDIC.

In case the data driver DDR is implemented in the COF type, each sourcedriving integrated circuit SDIC served as the data driver DDR may bemounted on a source side circuit film SF.

One side of the source side circuit film SF may be electricallyconnected to the pad, such as an array of pads, disposed in thenon-active area N/A.

One or more lines electrically connecting between the source drivingintegrated circuit SDIC and the panel PNL may be arranged on the sourceside circuit film SF.

For circuit connections between the plurality of source drivingintegrated circuits SDIC and other units or electronic elements, thedisplay device may include one or more source printed circuit boardSPCB, and a control printed circuit board CPCB for mounting severalunits used for controlling the display device and otherelements/units/devices.

The other side of the source side circuit film SF in which the sourcedriving integrated circuit SDIC is mounted may be connected to the oneor more source printed circuit board SPCB.

That is, the one side and the other side of the source side circuit filmSF contained of the source driving integrated circuit SDIC may beelectrically connected to the non-active area N/A of the panel PNL andthe one or more source printed circuit board SPCB, respectively.

The controller CTR for controlling the data driver DDR, the gate driverGDR, or the like may be disposed on the control printed circuit boardCPCB.

In addition, the control printed circuit board CPCB may further includea power management integrated circuit PMIC that provides variousvoltages or currents or controls various voltages or currents to beprovided, to the panel PNL, the data driver DDR, the gate driver GDR,and the like.

The source printed circuit board SPCB and the control printed circuitboard CPCB may be connected to each other in a circuit through at leastone connection unit CBL. Here, connection unit CBL may be a flexibleprinted circuit FPC, a flexible flat cable, or the like.

One or more source printed circuit board SPCB and the control printedcircuit board CPCB may be integrated into one printed circuit board.

In case the gate driver GDR is implemented in the gate in panel GIPtype, a plurality of gate driving circuits GDC included in the gatedriver GDR may be directly formed in the non-active area N/A of thepanel PNL.

Each of the plurality of gate driving circuits GDC may output scansignals to corresponding gate lines arranged in the active area A/A ofthe panel PNL.

The plurality of gate driving circuits GDC arranged in the panel PNL mayreceive various signals (a clock signal, a high level gate voltage VGH,a low level gate voltage VGL, a start signal VST, a reset signal RST, orthe like) needed for generating the scan signals throughgate-driving-related lines disposed in the non-active area N/A.

The gate-driving-related lines disposed in the non-active area N/A maybe electrically connected to the source side circuit film SF disposedclosest to a plurality of gate driving circuits GDC.

FIG. 3 is a view illustrating a structure of a subpixel arranged in anorganic light emitting diode OLED panel, according to embodiments of thepresent disclosure. Referring to FIG. 3, each subpixel SP in the OLEDpanel 110 may be implemented by electronic elements including, but notlimited to, an organic light emitting diode OLED, a driving transistorDRT for driving the organic light emitting diode OLED, a switchingtransistor O-SWT electrically connected between a first node N1 of thedriving transistor DRT and a corresponding data line DL, a storagecapacitor Cst electrically connected between the first node N1 and asecond node N2 of the driving transistor DRT, or the like.

The organic light emitting diode OLED may include an anode electrode, anorganic light emitting layer, a cathode electrode, and the like.

Referring to FIG. 3, an anode electrode (also referred to as a pixelelectrode) of the organic light emitting diode OLED may be electricallyconnected to a second node N2 of a driving transistor DRT. A low voltageEVSS may be applied to a cathode electrode (also referred to as a commonelectrode) of the organic light emitting diode OLED.

Herein, the low voltage EVSS may be a ground voltage or a voltage higheror lower than the ground voltage. In addition, a value of the lowvoltage EVSS may be varied depending on a driving state. For example,values of low voltage EVSS when image driving is performed and whensensing driving is performed may be differently set from each other.

The driving transistor DRT drives the organic light emitting diode OLEDby providing driving currents to the organic light emitting diode OLED.

The driving transistor DRT may include a first node N1, a second node N2a third node N3, and the like.

The first node N1 of the driving transistor DRT may be a gate node, andmay be electrically connected to a source node or a drain node of theswitching transistor O-SWT. The second node N2 of the driving transistorDRT may be a source node or a drain node, and electrically connected tothe anode electrode (or cathode electrode) of the organic light emittingdiode OLED. The third node N3 of the driving transistor DRT may be thedrain node or the source node. A driving voltage EVDD may be applied tothe third node N3 that may be electrically connected to a drivingvoltage line DVL providing the driving voltage EVDD.

The storage capacitor Cst may be electrically connected between thefirst node N1 and the second node N2 of the driving transistor DRT andmay maintain a data voltage Vdata corresponding to an image signalvoltage or a corresponding voltage for one frame time (or apre-configured time).

The drain node or the source node of the switching transistor O- SWT iselectrically connected to a corresponding data line, and the source nodeor the drain node of the switching transistor O-SWT is electricallyconnected to the first node N1 of the driving transistor DRT, and thegate node of the switching transistor O-SWT is electrically connected toa corresponding gate line, and thereby can receive scan signal SCAN.

On-off operation of the switching transistor O-SWT may be controlled bya scan signal SCAN input to the gate node of the switching transistorO-SWT through a corresponding gate line.

The switching transistor O-SWT may be turned on by the scan signal SCAN,may transfer a data voltage Vdata provided from a corresponding dataline DL to the first node N1 of the driving transistor DRT.

Meanwhile, the storage capacitor Cst may be an external capacitorconfigured to be located outside of the driving transistor DRT otherthan an internal capacitor, that is, a parasitic capacitor (e.g., Cgs,Cgd), that presents between the first node N1 and the second node N2 ofthe driving transistor DRT.

Each of the driving transistor DRT and the switching transistor O- SWTmay be an n-type transistor or a p-type transistor.

As shown in FIG. 3, two transistors (2T) and one capacitor (1C) type ofsubpixel structure is discussed for convenience of discussion, but theembodiments are not limited thereto. In some embodiments, the subpixelmay further include one or more transistors and/or one or morecapacitors. In some embodiments, a plurality of subpixels may have anidentical structure, or one or more of the plurality of subpixels mayhave different structure from others.

FIG. 4 is a cross-sectional view illustrating the display deviceaccording to embodiments of the present disclosure. Referring to FIG. 4,the display panel according to embodiments of the present disclosure mayinclude a substrate SUB, an overcoat layer OC located over thesubstrate, an anode electrode ANO located on the overcoat layer, a banklayer BNK located on a reflective electrode, an organic light emittinglayer EL located on the reflective electrode, and a cathode electrodeCAT located on the organic light emitting layer and the bank layer.

The overcoat layer OC may be referred to as a planarization layer forenabling one or more pixels to be arranged over an array of transistors.The overcoat layer may include a first area A1 (also referred to as a“first flat area” herein), a second area A2 and an inclined area SA. Apart of the second area A2 adjacent to the inclined area SA and having atop flat surface is referred to as a “second flat area” herein.

The second area A2 may be thicker than the first area A1. The secondarea A2 may be an area surrounding the first area. The inclined area SAmay be located between the first area and the second area, and mayinclude a first inclined surface S1 connecting between the first areaand the second area.

In defining a thickness of each area of the overcoat layer, thethickness of each area means the thickness of the overcoat layerdisposed over the substrate of the transistor. The thickness of eacharea may be defined as the thickness of the overcoat layer measuredbetween a passivation layer PAS disposed directly under the overcoatlayer OC and the anode electrode ANO disposed directly on the overcoatlayer OC, in each area. In particular, the thickness of each area may bedefined as the thickest thickness of the overcoat layer measured in eacharea except for a portion in which a contact hole, or the like isintroduced.

As shown in FIG. 4, the thickness of the first area T1 may be smallerthan that of the second area T2. Therefore, the first area A1 may form aconcave portion of the overcoat layer and the second area A2 may form aconvex portion of the overcoat layer.

The overcoat layer including the first area A1, the second area A2 andthe inclined area SA may be formed through a photolithography processusing a half-tone mask

A shape of the first area A1 may be, but not limited to, a polygonalshape such as a circle or a square, a pentagon, and an octagon. Thesecond area A2 may surround the first area A1, and may form a side wallsurrounding the side portion of the first area A1 having the shapedescribed above.

Both the first area A1 and the second area A2 may be connected to theinclined area SA formed by a difference between thickness of the firstarea A1 and the thickness of the second area A2. The inclined area SAmay include the first inclined surface S1.

Accordingly, the overcoat layer may have a shape such that the secondarea A2 having the convex portion surrounds around the first area A1having the concave portion, and the first area A1 and the second area A2are connected to each other by the inclined area S1 having apre-configured degree and height.

The anode electrode ANO may be located on the overcoat layer OC andformed along the surface of the overcoat layer.

This forming of the anode electrode ANO along the surface of theovercoat layer OC may mean that the reflective electrode is formed onthe overcoat layer with a thickness that is considered to be uniformwhen a thickness variation due to a tolerable process deviation is takeninto account.

As described above, the overcoat layer may have a shape such that thesecond area A2 having the convex portion surrounds around the first areaA1 having the concave portion, and the first area A1 and the second areaA2 are connected to each other by the inclined surface S1 having apre-configured degree and height. In case the reflective electrode isformed along the surface of the overcoat layer as described above, thereflective electrode has a similar shape to the overcoat layer. Thus,the reflective electrode may have a shape such that the inclined surfaceSi having a pre-configured angle and height surrounds the concaveportion of the reflective electrode.

Accordingly, in case the anode electrode ANO is formed along the surfaceof the overcoat layer OC, the reflective electrode may include thesecond inclined surface S2 located on the first inclined surface S1.

This locating of the second inclined surface S2 on the first inclinedsurface S1 may mean that since the anode electrode ANO is formed alongthe surface of the overcoat OC, the second inclined surface S2 is formedalong the first inclined surface S1.

The anode electrode ANO may be electrically connected to a drainelectrode D or a source electrode S of a transistor TR through a contacthole.

The anode electrode may be an electrode including the reflectiveelectrode. The anode electrode may include a conductive metal oxidelayer including indium tin oxide ITO and a reflective metal layerincluding silver. For example, the anode electrode may include a firstindium tin oxide ITO layer located on the overcoat layer, the reflectivemetal layer including silver located on the first indium tin oxide ITOlayer, and a second indium tin oxide ITO layer located on the reflectivemetal layer.

The bank layer BNK may be located on the anode electrode ANO, and at thesame time, may be located on the second area A2, the inclined area SAand the first area A1 connected to the inclined area SA. The bank layerBNK may further include a third inclined surface S3 formed along thesecond inclined surface S2.

The bank layer BNK includes the third inclined surface S3 formed alongthe second inclined surface S2 of the reflective electrode formed alongthe first inclined surface Si of the overcoat layer OC. Therefore, thebank layer may be formed on the second area A2 forming the convexportion of the overcoat layer and the first inclined area Si of theovercoat layer, resulting in the first area A1 forming the concaveportion of the overcoat layer being surrounded by the bank layer.

The organic light emitting layer EL may be located on a portion of theanode electrode which is not covered by the bank layer, and may belocated on the first area A1.

The cathode electrode CAT may be located on the organic light emittinglayer EL and the bank layer BNK. The display panel may be a top emissiontype in which light emitted from the organic light emitting layer isemitted through the cathode electrode CAT. Accordingly, the cathodeelectrode CAT may be a transparent electrode with excellenttransmittance to light in the visible light region, and the bank layerBNK may perform a function as a layer for distinguishing between anopening area OPN and a non-opening area NOP of the display panel.

As described above, the display panel in the present disclosure mayinclude two areas that are the opening area OPN and the non-opening areaNOP caused by the configuration of the bank layer BNK. The opening areaOPN may correspond to an area that is not covered by the bank layer, andthe non-opening area NOP may correspond to an area that is covered bythe bank layer.

The correspondence of an area to another area may mean a relationship inwhich an area and another area are considered to be the same, takinginto account tolerance that may occur in the manufacturing process of aproduct.

As described above, the anode electrode ANO, the bank layer BNK, theorganic light emitting layer EL and the cathode electrode CAT arelocated over the overcoat layer OC, and therefore light emitting may beperformed in the first area A1 of the overcoat layer in which the anodeelectrode ANO, the organic light emitting layer EL and the cathodeelectrode CAT are sequentially stacked. In addition, a portion of thefirst area A1 of the overcoat layer in which the anode electrode ANO,the organic light emitting layer EL and the cathode electrode CAT aredisposed in order is the opening area OPN that is not covered by thebank layer BNK, and therefore light emitting may be performed in theorganic light emitting layer EL by the anode electrode ANO exposed tothe opening area OPN of the bank layer BNK and electric field formed bythe cathode electrode CAT.

On the other hand, light is not emitted from organic light emittinglayer EL in an area in which the bank layer BNK is present between theorganic light emitting layer EL and the anode electrode ANO due to thebank layer BNK.

In accordance with embodiments of the present disclosure, the displaypanel may include a buffer layer BUF, an interlayer insulating film INF,a passivation layer PAS, a transistor TR, a storage capacitor C1, C2, anauxiliary electrode (AE, or may be referred to as an auxiliary line),and pad area.

The buffer layer BUF may be disposed on the substrate SUB, and thetransistor TR and the storage capacitor C1, C2, and the like may bedisposed over the buffer layer BUF.

The interlayer insulating film INF may be located on a gate electrodeGATE of the transistor TR, an active layer ACT, a first storagecapacitor C1 of the storage capacitor, and a first pad electrode P1 ofthe pad area.

The passivation layer PAS may be disposed to protect an electric circuitelement, such as the auxiliary electrode AE, the storage capacitor C1,C2, the transistor TR, and the like.

The transistor TR may include the activation layer ACT, a gateinsulating film GI, a gate electrode GATE, a source electrode S and adrain electrode D. Hereinafter, discussions are conducted on atransistor according to embodiments of the present disclosure. Typicalimplementations performed in the field of the present disclosure may beused to describe a location relationship between respective elements ofthe transistor in the present disclosure.

The activation layer ACT may be disposed on the buffer layer BUF.

The gate insulating film GI is disposed on the activation layer ACT, andthe gate electrode GATE is disposed on the gate insulating film GI.Therefore, the gate insulating film GI may be located between theactivation layer ACT and the gate electrode GATE.

Each of the source electrode S and the drain electrode D may be disposedon respective portions of the activation layer ACT, and spaced apartfrom each other. The drain electrode D may be connected to the firstelectrode ANO through a contact hole CH. By placing the contact hole CHin the second area A2, which is outside the first area A1 on which thefirst electrode ANO comes into contact with the organic light emittinglayer (EL), the presence of the contact hole CH does not negativelyaffect the flatness of the first electrode ANO. Hence, the lightemission quality of the subpixels are maintained consistent and reliablycompared to cases where the contact hole CH is located in the first areaA1. At least a portion of the bank layer BNK is inserted into thecontact hole CH on the first electrode ANO. A depth T3 of the bank layerBNK from the top of the bank layer BNK to the bottom of the contact holeCH is larger than the thickness T1 of the overcoat layer OC and thethickness T2 of the overcoat layer OC.

The transistor TR may function as a driving transistor DRT included inthe panel, and drive the OLED included in the panel. By placing at leasta portion of the transistor TR in the first area A1 instead of placingthe transistor TR only in the second area A2 (as illustrated in FIG. 4),space in the second area A2 may become available to accommodate othercircuit components such as other transistors, wires and capacitors inthe second area A2. Therefore, such placement of the transistor TR mayfacilitate increase in the density of the subpixels.

As shown in FIG. 4, the storage capacitor C1, C2 may be disposed in theactive area A/A. The storage capacitor C1, C2 may include a firststorage capacitor electrode C1 disposed in an identical layer to thegate electrode GATE and a second storage capacitor electrode C2 disposedin an identical layer to the source electrode S and the drain electrodeD, but the structure of the storage capacitor C1, C2 of the presentdisclosure is not limited thereto. The storage capacitor C1, C2 isplaced at least partially placed in the first area A1. This isadvantageous, among other reasons, because space is made in the secondarea A2 to accommodate other circuit components in the second area A2,and thereby facilitate the increase of the density of subpixels.

In addition, as shown in FIG. 4, the auxiliary electrode AE contacted tothe anode electrode ANO may be further disposed in the active area A/A.

Specifically, the auxiliary electrode AE may be disposed on theinterlayer insulating film INF. The passivation layer PAS, an overcoatlayer OC and the bank layer BNK may have a hole that does not cover theauxiliary electrode AE. The cathode CAT may contact the auxiliaryelectrode AE through the hole of the passivation layer PAS, overcoatlayer OC and the bank layer BNK.

For example, in case the organic light emitting display panel is adisplay panel having a large size, voltage drop due to the resistance ofthe anode electrode ANO may occur, resulting in a luminance differencebetween the outer edge and the center of the panel. However, in theorganic light emitting display panel according to the presentdisclosure, it is possible to overcome voltage drop occurring throughthe auxiliary electrode AE contacted to the anode electrode ANO. Thus,in case the organic light emitting display panel according toembodiments of the present disclosure is a panel having a large size, itis possible to prevent the panel from the occurrence of the luminancedifference.

FIG. 4 shows that one auxiliary electrode AE is disposed in one subpixelSP, but present disclosure is not limit thereto. For example, oneauxiliary electrode AE may be disposed per a plurality of subpixels SPbasis. In one or more embodiments, the auxiliary electrode AE may beconnected to subpixel SP only at the edges of the display panel.

As another example, in case the organic light emitting display panelaccording to embodiments of the present disclosure is not a panel havinga large size, the panel may not include the auxiliary electrode AE.

In addition, the display panel according to embodiments of the presentdisclosure may include a pad area disposed in the non-active area. Aplurality of pad electrodes P1 and P2 may be disposed in the pad area.For example, a first pad electrode P1 may be disposed on a plurality ofinsulating films BUF and GI disposed in the pad area. The interlayerinsulating film INF that does not cover a portion of a top surface ofthe first pad electrode P1 may be disposed on the first pad electrodeP1. A second pad electrode P2 contacted to the first pad electrode P1may be disposed on the first pad electrode P1 and the interlayerinsulating film INF.

FIG. 4 also illustrates a viewing plane VP at which the light emittedfrom the display panel is captured. The viewing plane may be located ata distance from the display panel. An example of the image representinglight emitted from the display panel is illustrated in FIG. 7B.

Although not shown in FIG. 4, various circuit films, or the like may beelectrically connected to the second pad electrode P2.

A viewing plane VP is illustrated in FIG. 4. The viewing plane VP is aplane onto which the light from the display is projected. The lightprojected onto the viewing plane VP is illustrated in FIG. 7B.

FIG. 5 is a view illustrating that light emitted from an organic lightemitting layer of the display panel reflected from a second inclinedsurface, according to embodiments of the present disclosure. Referringto FIG. 5, light emitted from the organic light emitting layer EL isemitted in various directions without directionality. In particular,some of the light emitted from the organic light emitting layer EL mayundergo total reflection and travel toward third inclined surface S3 ofthe bank layer BNK, while traveling from a layer (not shown) with a highrefractive index to a layer (not shown) with a low refractive index.

The bank layer BNK is formed from a material that is transparent tovisible light wavelength band. Accordingly, light emitted toward thethird inclined surface S3 of the bank layer BNK may go through the thirdinclined surface S3 of the bank layer BNK, and then reach the secondinclined surface S2 of the anode electrode ANO.

Light having reached the second inclined surface S2 of the anodeelectrode ANO is reflected from the second inclined surface S2, and thenmay travel toward the third inclined surface S3 of the bank layer BNKand exit the display panel. Accordingly, as described above, in thedisplay panel according to embodiments of the present disclosure, thesecond inclined surface S2 of the reflective electrode formed on thefirst inclined surface S1 enables light emitted from the organic lightemitting layer EL to travel toward an upper portion of the displaypanel, resulting in improvement in the luminous efficiency of thedisplay panel.

FIG. 6 is an expanded cross-sectional view of the first inclined surfaceS1, the second inclined surface S2 and the third inclined surface S3 ofthe display device according to embodiments of the present disclosure.Referring to FIG. 6, an angle between the first area A1 and the firstinclined surface S1 is represented as θ (hereinafter, referred to as“θ”), a horizontal distance between the second inclined surface S2 andthe third inclined surface S3 is represented as d (hereinafter, referredto as “d”), and a vertical height of the inclined area SA is representedas h (hereinafter, referred to as “h”). According to embodiments of thepresent disclosure, it is possible to provide a display panel withincreased luminous efficiency by adjusting the θ and the d, or the θ,the d and the h.

The angle θ between the first area A1 and the first inclined surface S1may be larger than or equal to 27° or 45°. There is no restriction tothe upper limit of the θ range. In this case, when the θ has a largervalue, the possibility that cracks and breaks occur in the anodeelectrode ANO formed on the overcoat layer is increased. Accordingly,the upper limit may be preferably less than or equal to 80° or 85°.

By keeping θ within this range, it is possible for the second inclinedsurface S2 to effectively reflect the light emitted from the organiclight emitting layer. Thus, it is possible to provide a display panelwith increased luminous efficiency.

The horizontal distance d between the second inclined surface S2 and thethird inclined surface S3 may be defined as a distance from the secondinclined surface S2 to the third inclined surface S3, measured inparallel direction to the first area A1 of the overcoat layer. Distanced may be may be less than or equal to 3.2 μm, 2.6 μm or 2.0 μm. Thesmaller the d is, the greater the opening area OPN of the display panelexpands. In this case, traveling paths of light reflected from thesecond inclined surface S2 may be reduced, and thus, luminous efficiencymay be increased. To this end, there is no restriction to the lowerlimit of the d. The lower limit of the d may be preferably larger thanor equal to 0.1 μm, 0.3 μm, or 0.5 μm. By adjusting the d range withinthis range, it is possible to expand an opening area and provide adisplay panel with increased luminous efficiency.

The vertical height h of the inclined area SA may denote a differencebetween the thickness T1′ of the first area A1 portion and the thicknessT2′ of the second area A2 portion, which are connected by the inclinedarea SA. The vertical height h may be preferably larger than or equal to0.7 μm, 1.2 μm, 1.4 μm, or 2 μm. The larger the h is, the greater theluminous efficiency increases because light emitted from the organiclight emitting layer EL by the second inclined surface S2 is reflectedeffectively. To this end, there is no restriction to the upper limit ofthe h. The upper limit may be preferably less than or equal to 10 μm, or5 μm.

As described above, by adjusting d, θ and h, the display panel accordingto the present disclosure provides increased luminous efficiency and mayinclude the first light emitting area and the second light emitting areawhen organic light emitting layer emits light.

FIGS. 7A and 7B are views showing an opening area, a non-opening area, afirst light emitting area, and a second light emitting area included inthe display panel, according to embodiments of the present disclosure.FIG. 7A shows a photomicrograp of the display panel inclining theopening area OPN and the non-opening area NOP having a specific shape.FIG. 7B is a view illustrating an image of the display panel including afirst light emitting area, and a second light emitting area capturedfrom the viewing plane VP.

The display panel according to the present disclosure may include afirst light emitting area LEA1 (also referred to as a “main lightemitting area”) and a second non-light emitting area NEA2, in whichvisible light is emitted when the organic light emitting layer emitslight, and a first non-light emitting area NEA1 and a second non-lightemitting area NEA2.

The first light emitting area LEA1 may have a shape corresponding to theshape of the opening area OPN. The correspondence of a shape of anelement to a shape of another element may mean that i) a shape of anelement is an identical shape to another element, ii) two elements havean identical shape, but have different sizes from each other, or iii) ashape of an element may be formed by transferring the shape of anotherelement. Accordingly, the shape of the first light emitting area LEA1may mean that the shape of the opening area OPN is substantiallytransferred by light emitted from the organic light emitting layer ELlocated in the opening area OPN.

There is no restriction to the shape of the opening area OPN. The shapeof the opening area OPN may preferably be, but not limited to, apolygonal shape such as a circle or a square, a pentagon, and anoctagon. Referring to FIG. 7A, the opening area OPN has an octagonalshape.

The first light emitting area LEA1 may have a shape corresponding to theopening area OPN. Referring to FIG. 7B, the first light emitting areaLEA1 has a shape corresponding to the shape of opening area OPN as shownin FIG. 7A.

The second light emitting area LEA2 ((also referred to as a“supplemental light emitting area”) may not overlap with or separatedfrom the first light emitting area LEA1 and may surround the first lightemitting area LEA1. The second light emitting area LEA2 may have a shapecorresponding to an edge shape of the first light emitting area LEA1. Asshown in FIG. 7B, the second light emitting area LEA2 has a shapeidentical to the edge of the first light emitting area LEA1, but hasdifferent size from the first light emitting area LEA1. Therefore, it ispossible to express that the second light emitting area LEA2 has a shapecorresponding to the edge shape of the first light emitting area LEA1.The second light emitting area LEA2 may be a closed curve having anidentical shape to the edge of the first light emitting area LEA1. Asanother example, the second light emitting area LEA2 may have a shape inwhich a portion of the closed curve is disconnected.

A plurality of subpixels may be distinguished by the first non-lightemitting area NEA1. Referring to FIG. 7B, each of a plurality of secondlight emitting area LEA2 may be spaced apart from another by the firstnon-light emitting area NEA1. That is, the first non-light emitting areaNEA1 may be an area between the second light emitting areas LEA2 in thenon-opening area NOP.

That is, the first non-light emitting area NEA1 may be substantially anarea from which light is not emitted. That is, the first non-lightemitting area NEA1 may correspond to a portion in which the second lightemitting area LEA2 is not formed in the non-opening area NOP.

The second non-light emitting area NEA2 may distinguish the first lightemitting area LEA1 and the second light emitting area LEA2 formed by thesubpixel and may be an area from which light is not substantiallyemitted.

The shape of the second non-light emitting area NEA2 may be determineddepending on the shapes of the first light emitting area LEA1 and thesecond light emitting area LEA2. For example, in case the first lightemitting area LEA1 has an octagonal shape, and the second light emittingarea LEA2 has a closed curve with the octagonal shape, the secondnon-light emitting area NOP2 may have the octagonal shape by the firstlight emitting area LEA1 and the second light emitting area LEA2.

Although the second non-light emitting area NEA2 is described using theterm of non-light emitting, it is possible for some light to be detectedin the photograph because the second non-light emitting area NEA2 islocated between the light emitting areas LEA1 and LEA2. In particular,it is possible for light with colors similar to a wavelength band ofvisible light emitted in the subpixel to be detected. Accordingly, thesecond non-light emitting area NEA2 may be an area from which light isnot emitted at all. Alternatively, it should be understood that thesecond non-light emitting area NEA2 may be an area from which lightweaker than what is emitted from the two light emitting areas isobserved.

As described above, the second light emitting area LEA2 may beimplemented by adjusting a range of θ, d, or h. Accordingly, the displaypanel according to embodiments of the present disclosure may haveincreased luminous efficiency and include the first light emitting areaLEA1 and the second light emitting area LEA2, by adjusting a range ofthe θ, the d, or the h.

It is estimated that the second light emitting area LEA2 is formed bylight traveling through paths described with reference to FIG. 5. Thedisplay panel according to embodiments of the present disclosureincludes, as well as the first light emitting area LEA1, but the secondlight emitting area LEA2 formed by light reflected from the secondinclined surface S2. Therefore, the display panel may have increasedluminous efficiency.

The second light emitting area may be located in such a way that thesecond light emitting area surrounds the first light emitting area. Thisis estimated from, as a main reason, that the second light emitting areaLEA2 is formed by light reflected from the second inclined surface S2 ofthe anode electrode ANO formed in the first inclined surface Si locatedin the inclined area SA surrounding the first area A1.

In addition, the second light emitting area LEA2 may be located in thenon-opening area NOP. As another embodiment, the overcoat layer may notinclude the inclined area, other than the display panel according toembodiments described above. In this case, among light emitted from theorganic light emitting layer, only some of light traveling toward theopening area exits the display panel, and light traveling toward thenon-opening area in which the bank layer is formed may be trapped withinthe display panel. Thus, in such display panels, light emitting area isobserved in only the opening area.

However, as shown in FIG. 5, in the display panel according toembodiments of the present disclosure, among light emitted from theorganic light emitting layer EL, light traveling toward the non-openingarea is reflected from the second inclined surface S2 and goes out ofthe display panel, and therefore second light emitting area (LEA2) maybe formed in the non-opening area NOP in which the bank layer isdisposed, by the reflected light.

As shown in FIG. 5, the light from the first light emitting area LEA1and the light from the second light emitting area LEA2 travel differentpaths and goes through different layers, and therefore may havedifferent color coordinates. Accordingly, a color coordinate of visiblelight emitted from the first light emitting area may be different from acolor coordinate of visible light emitted from the second light emittingarea adjacent to the first light emitting area. As shown in FIG. 7B, aplurality of the first light emitting areas and the second lightemitting areas may be formed according to the number of subpixelsincluded in the display panel. Thus, it should be understood that thesecond light emitting area adjacent to the first light emitting area isa light emitting area included in an identical subpixel area, anddenotes the second light emitting area adjacent to the first lightemitting area of a plurality of the second light emitting area.

FIG. 8 is a cross-sectional view illustrating the display deviceaccording to embodiments of the present disclosure. Referring to FIG. 8,the organic light emitting layer EL may be located on a portion of theanode electrode ANO that is not covered by the bank layer BNK and thebank layer BNK, and the cathode electrode CAT may be located on theorganic light emitting layer EL.

Table 1 below shows data on the luminous efficiency measured inComparative examples and Embodiments.

Display panels used for the Embodiments have a structure as shown inFIG. 8. Each display panel in the Embodiments have identicalconfigurations to others, except for being configured with the θ, the dand the h described in the Table 1. A display panel in the Comparativeexample has identical configurations to display panels in theEmbodiments except for not including the first inclined surface to thirdinclined surface.

TABLE 1 luminous θ(°) h(μm) d(μm) efficiency(Cd/A) Comparative — — —55.5 example 1 Embodiment 1 42 2 2.3 62.2 Embodiment 2 34 2 3.2 58.0Embodiment 3 40 2 4.4 59.4 Embodiment 4 44 2 5.2 59.0

In the Table 1, in case of Comparative example 1, there are no values ofthe θ, the h and the d because the first inclined surface to the thirdinclined surface are not included. It can be seen that luminousefficiency in the Embodiments 1 to 4 increases more than that inComparative examples, and in particular, luminous efficiency in theEmbodiments 1 and 2 with the d less than or equal to 3.2 μm increasemore than that in the Embodiments 3 and 4. In particular, it can beobserved that the Embodiment 1 in which the d less than or equal to 2.3μm shows the most increased luminous efficiency.

In case the organic light emitting layer EL is disposed in, as well asthe opening area OPN in which the bank layer BNK is not disposed, butthe non-opening area NOP in which the bank layer BNK is disposed, it ispossible to maximize the area of the organic light emitting layer EL inwhich light emitting is performed. In case the organic light emittinglayer EL is disposed in only the opening area OPN, due to limitations inprocess, the organic light emitting layer EL may not be formed in anedge portion of the opening area OPN or may be incompletely formed.However as described above, in case the organic light emitting layer ELis disposed on the bank layer BNK, it is possible to overcome someproblems with limitations in process.

Table 2 below shows data related to whether the second light emittingarea is included according to the θ, the d and the h.

TABLE 2 Whether the second light emitting area θ(°) h(μm) d(μm) isdisposed Comparative 8.0 0.60 2.0 X example 2 Comparative 25.0 1.70 2.0X example 3 Comparative 25.8 1.70 2.0 X example 4 Embodiment 5 45.0 1.402.0 O Embodiment 6 60.0 2.00 2.0 O Embodiment 7 60.0 2.04 2.0 O

The Comparative examples 2 and 3 and the Embodiments 4 to 7 are based onthe display panel as shown in FIG. 4 and have identical configurationsexcept for different θs and hs as described in Table 2.

Referring to Table 2, it can be seen that, in case the display panel isconfigured with a larger θ and a larger h, the second light emittingarea is formed because the second inclined surface of the reflectiveelectrode can effectively reflect light emitted from the organic lightemitting layer.

In case the organic light emitting layer EL is formed as shown in FIG.8, a first light emitting layer emitting a first color and a secondlight emitting layer emitting a second color may be disposed on theanode electrode ANO and the bank layer BNK. In this case, each of thefirst light emitting layer emitting the first color and the second lightemitting layer emitting the second color is disposed in a differentopening area OPN distinguished by the bank layer BNK, it is possible toomit to use a large mask and to simplify a related process.

FIG. 9 is a cross-sectional view illustrating a part of the displaydevice according to embodiments of the present disclosure. Referring toFIG. 9, the thickness t1 of the organic light emitting layer EL disposedon the anode electrode ANO is larger than the thickness t2 of theorganic light emitting layer EL disposed on the third inclined surfaceS3 of the bank layer BNK.

The difference in the thicknesses of the organic light emitting layermay be caused by the third inclined surface S3 of the bank layer BNK.The organic light emitting layer EL may be formed by a thermalevaporation process, which is a physical vapor deposition technique. Incase the thermal evaporation process is used on the inclined surface,such as third inclined surface S3, the thickness of the deposited layermay be reduced due to characteristics of the thermal deposition process.

In case a portion of the organic light emitting layer is thinned, thedensity of carriers may be increased at an electrode adjacent to anorganic light emitting layer with a thin thickness and result in theorganic light emitting layer being deteriorated. However, it is possibleto prevent such problems in the display panel according to embodimentsof the present disclosure, as shown in FIG. 9, because the bank layerBNK is located between the reflective electrode EL and the organic lightemitting layer EL, in a portion in which the organic light emittinglayer EL has the thinned thickness t2.

Although a preferred embodiment of the present disclosure has beendescribed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims. Although the exemplaryembodiments have been described for illustrative purposes, a personskilled in the art will appreciate that various modifications andapplications are possible without departing from the essentialcharacteristics of the present disclosure. For example, the specificcomponents of the exemplary embodiments may be variously modified. Thevarious embodiments described above can be combined to provide furtherembodiments. These and other changes can be made to the embodiments inlight of the above-detailed description. In general, in the followingclaims, the terms used should not be construed to limit the claims tothe specific embodiments disclosed in the specification and the claims,but should be construed to include all possible embodiments along withthe full scope of equivalents to which such claims are entitled.Accordingly, the claims are not limited by the disclosure.

What is claimed is:
 1. An organic light emitting display panelcomprising: a substrate including an active area and a non-active area,the non-active area including a pad area; a transistor in the activearea of the substrate, the transistor comprising a first node, a secondnode, and a third node; an insulating film disposed over the transistorin the active area of the substrate, the insulating film including atleast one hole; a sub-pixel electrically connected to the transistor,the sub-pixel including a plurality of light emitting areas and aplurality of separation areas in the active area of the substrate; and aplurality of pad electrodes disposed in the pad area, the plurality ofpad electrodes comprising a first pad electrode and a second padelectrode, wherein the plurality of pad electrodes in the pad area aredisposed on a same layer with each of the first node, the second node,and the third node in the active area.
 2. The organic light emittingdisplay panel according to claim 1, wherein the sub-pixel comprises afirst electrode, an organic emitting layer, and a second electrode onthe insulating film.
 3. The organic light emitting display panelaccording to claim 2, further comprising a bank layer disposed on theinsulating film and partially on the first electrode, the bank layerhaving a first inclined surface and a second inclined surface disposedin a concavity of the insulating film.
 4. The organic light emittingdisplay panel according to claim 1, wherein the second node or the thirdnode of the transistor and the first electrode are electricallyconnected in the at least one hole of the insulating film.
 5. Theorganic light emitting display panel according to claim 1, furthercomprising an auxiliary electrode disposed in a separation area from theplurality of separation areas, the auxiliary electrode on a same layerwith the first pad electrode in the pad area, and the first node in theactive area.
 6. The organic light emitting display panel according toclaim 5, wherein the auxiliary electrode contacts the second electrodein the at least one hole of the insulating film.
 7. The organic lightemitting display panel according to claim 1, wherein each of the firstpad electrode and the second pad electrode in the pad area are disposedon the same layer with each of the first node and the second node or thethird node in the active area, respectively.
 8. The organic lightemitting display panel according to claim 7, further comprising aninterlayer insulating film on the substrate, the interlayer insulatingfilm disposed on the first pad electrode without covering a portion of atop surface of the first pad electrode.
 9. The organic light emittingdisplay panel according to claim 8, wherein the second pad electrode isdisposed on the interlayer insulating film and contacts the first padelectrode in the pad area.
 10. The organic light emitting display panelaccording to claim 1, further comprising a gate insulating film disposedon the first node in the active area and on the first pad electrode inthe pad area.
 11. The organic light emitting display panel according toclaim 10, further comprising an activation layer disposed on thesubstrate in the active area, the activation layer disposed between thesubstrate and the gate insulating film.
 12. The organic light emittingdisplay panel according to claim 3, wherein the bank layer comprises athird inclined surface, a fourth inclined surface, and a fifth inclinedsurface in a separation area from the plurality of separation areas. 13.The organic light emitting display panel according to claim 12, whereinthe third inclined surface and the fourth inclined surface of the banklayer is in a first hole of the insulating film, and the fifth inclinedsurface of the bank layer in in line with an inclined surface of theinsulating film in a second hole of the insulating film.
 14. The organiclight emitting display panel according to claim 13, wherein the secondelectrode is disposed on the fifth inclined surface of the bank layerand the inclined surface of the insulating film in the second hole ofthe insulating film.
 15. The organic light emitting display panelaccording to claim 12, wherein the first electrode contacts the firstinclined surface of the bank layer in the at least one of the pluralityof light emitting areas, and contacts the third inclined surface and thefourth inclined surface of the bank layer in at least one of theplurality of separation areas.
 16. The organic light emitting displaypanel according to claim 1, wherein the first electrode is disposed inthe plurality of light emitting areas and the plurality of separationareas.
 17. The organic light emitting display panel according to claim8, wherein the interlayer insulating film is disposed on the first nodeof the transistor in the active area, the interlayer insulating filmcovering a top surface of the first node.
 18. The organic light emittingdisplay panel according to claim 1, further comprising a storagecapacitor disposed on the substrate in the active area, the storagecapacitor comprising a first storage capacitor and a second storagecapacitor, wherein each of the first pad electrode and the second padelectrode in the pad area are disposed on a same layer with each of thefirst storage capacitor and the second storage capacitor in the activearea, respectively.
 19. The organic light emitting display panelaccording to claim 18, further comprising a passivation layer coveringthe storage capacitor in the active area.
 20. The organic light emittingdisplay panel according to claim 19, wherein the plurality of the padelectrodes in the pad area are not covered by the passivation layer. 21.The organic light emitting display panel according to claim 19, whereinthe passivation layer partially covers the second node or the third nodeof the transistor of the sub-pixel.
 22. The organic light emittingdisplay panel according to claim 6, further comprising a passivationlayer disposed on the transistor of the sub-pixel, the passivation layerpartially covering the auxiliary electrode.